1. Field of the Invention
The present invention relates generally to integrated circuit memory devices, and more specifically to a circuit and method for preventing false parity errors in certain types of memory devices.
2. Description of the Prior Art
As is well known, occasional errors can occur in data stored in semiconductor memory devices. These errors can be caused by, for example, the malfunction of marginal active devices in an integrated circuit chip, electronic perturbations such as caused by power supply problems, and events such as ionization caused by alpha particle strikes. In most cases, the occurrence of these errors is essentially random. One common method used to detect the occurrence of such random errors is the generation and detection of a parity bit.
In its most common form, 1 parity bit is provided for each eight data bits, or for some other relatively small group of bits. Parity is defined as being odd or even, with the parity bit being assigned a value of 1 or 0 so that the number of ones in the data-plus-parity bits is either odd or even according to the defined parity scheme. This parity scheme allows for the detection of single bit errors, but will not detect two bit errors. In addition, no error correction is provided. Such a single bit parity detection scheme provides a good tradeoff between low cost and adequate error protection for most applications. This is true primarily because of the high reliability of semiconductor memory devices.
One type of memory used in computer systems is a cache memory. This is a relatively small, fast memory which resides in the system between the central processor and main system memory. Cache memory includes data memory fields for storing data cached from system memory, and tag memory fields for storing the addresses corresponding to the data stored in the data cache. Like other memories, cache memories typically include parity checking.
Some cache tag memory devices, such as that described in the application entitled DUAL-PORT CACHE TAG MEMORY, cited above, have two ports which can access a memory array asynchronously. In devices designed specifically for use as cache tag memories, one of the data ports can write data to a single bit of an entry in the array. This can cause the parity checking scheme to fail, since changing the value of a single bit would require the value of the parity bit to also be changed. In order to avoid this problem, it is possible to leave the single changeable bit out of the parity checking scheme, but this is undesirable since it does not provide for full parity checking of the memory.
In a dual port memory in which one port can change the value of a single bit of an entry in the memory, it would be desirable to provide a means for properly adjusting the parity bit of the entry so that parity checking remains valid, so that such single changeable bit can be included in the protection offered by the parity checker.